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ATWILC3000 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 datasheet description the atmel ? ATWILC3000 is a single chip ieee ? 802.11 b/g/n rf/baseband/mac link controller and bluetooth ? 4.0 optimiz ed for low - power mobile applications. the ATWILC3000 supports single stream 1x1 802.11n mode providing up to 72mbps phy rate. the ATWILC3000 features fully integrated power amplifier, lna, switch, and power management. implemented in 65nm cmos technology, the ATWILC3000 offers very low power consumption while simultaneously providing high performance and minimal bill of materials. the ATWILC3000 utilizes highly optimized 802.11 - bluetooth coexistence protocols. the ATWILC3000 provides multiple peripheral int erfaces including uart, spi, i 2 c, and sdio. the only external clock sources needed for the ATWILC3000 is a high - speed crystal or oscillator with a wide range of reference clock frequencies supported (14 - 40mhz) and a 32.768khz clock for sleep operation. the ATWILC3000 is available in both qfn and wafer level chip scale package (wlcsp) packaging. features ? ieee 802.11 b/g/n 20mhz (1x1) solution ? single spatial stream in 2.4ghz ism band ? integrated pa and t/r switch ? superior sensitivity and range via advanced phy signal processing ? advanced equalization and channel estimation ? advanced carrier and timing synchronization ? wi - fi direct and soft - ap support ? supports ieee 802.11 wep, wpa, and wpa2 security ? supports china wapi security ? superior mac throughput via hardware accelerated two - level a - msdu/a - mpdu frame aggregation and block acknowledgement ? on - chip memory management engine to reduce host load ? spi, sdio, i 2 c, and uart host interfaces ? operating temperature range of - 4 0c to +85c atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 2 2 bluetooth: ? bluetooth 4.0 (basic rate, enhanced rate and ble) ? class 1 and 2 transmission ? adaptive frequency hopping ? hci (host control interface) via high speed uart ? integrated pa and t/r switch ? superior sensitivity and range ? pcm audio interface
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 3 3 ta bl e of conte nts 1 ordering information and ic marking ................................ ................................ ........ 5 2 block diagram ................................ ................................ ................................ ............. 5 3 pinout and package information ................................ ................................ ................ 6 3.1 pin description ................................ ................................ ................................ ................................ ...... 6 3.2 package description ................................ ................................ ................................ ............................. 8 4 electrical specifications ................................ ................................ ........................... 10 4.1 absolute ratings ................................ ................................ ................................ ................................ . 10 4.2 recommended operating conditions ................................ ................................ ................................ . 10 4.3 dc electrical characteristics ................................ ................................ ................................ ............... 11 5 clocking ................................ ................................ ................................ ................... 12 5.1 cryst al oscillator ................................ ................................ ................................ ................................ . 12 5.2 low - power oscillator ................................ ................................ ................................ .......................... 13 6 cpu and memory subsystems ................................ ................................ ................. 14 6.1 processor ................................ ................................ ................................ ................................ ............ 14 6.2 memory subsystem ................................ ................................ ................................ ............................. 14 6.3 non - volatile memory (efuse) ................................ ................................ ................................ ............. 14 7 wlan subsystem ................................ ................................ ................................ ...... 16 7.1 mac ................................ ................................ ................................ ................................ .............. 16 7.1.1 features ................................ ................................ ................................ ................................ . 16 7.1.2 description ................................ ................................ ................................ .............................. 16 7.2 phy ................................ ................................ ................................ ................................ .............. 17 7.2.1 features ................................ ................................ ................................ ................................ . 17 7.2 .2 description ................................ ................................ ................................ .............................. 17 7.3 802.11 b/g/n radio performance ................................ ................................ ................................ ........ 17 7.3.1 receiver performance ................................ ................................ ................................ ............ 17 7.3.2 transmitter performance ................................ ................................ ................................ ........ 18 8 bluetooth subsystem ................................ ................................ ................................ 19 8.1 bluetooth 4.0 ................................ ................................ ................................ ................................ ....... 19 8.2 bluetooth low energy (ble) ................................ ................................ ................................ ............... 19 8.3 bluetooth radio ................................ ................................ ................................ ................................ ... 20 8.3.1 receiver performance ................................ ................................ ................................ ............ 20 8.3.2 transmitter performance ................................ ................................ ................................ ........ 20 9 external interfaces ................................ ................................ ................................ .... 21 9.1 i 2 c sl ave interface ................................ ................................ ................................ .............................. 21 9.2 i 2 c master interface ................................ ................................ ................................ ............................ 22 9.3 spi slave interface ................................ ................................ ................................ .............................. 23 9.4 spi master interface ................................ ................................ ................................ ............................ 25 9.5 sdio slave interface ................................ ................................ ................................ ........................... 27 9.6 uart ................................ ................................ ................................ ................................ .............. 28 9.7 pcm interface ................................ ................................ ................................ ................................ ..... 29 9.8 gpios ................................ ................................ ................................ ................................ .............. 29
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 4 4 10 power management ................................ ................................ ................................ ... 30 10.1 power architecture ................................ ................................ ................................ .............................. 30 10.2 power consumption ................................ ................................ ................................ ............................ 31 10.2.1 description of device states ................................ ................................ ................................ ... 31 10.2.2 current consumption in various device states ................................ ................................ ...... 31 10.2.3 restrictions for power states ................................ ................................ ................................ . 32 10.3 power - up/down sequence ................................ ................................ ................................ ................. 32 10.4 digital i/o pin behavior during power - up sequences ................................ ................................ ......... 33 11 reference design ................................ ................................ ................................ ...... 34 12 reference design guidelines ................................ ................................ ................... 35 13 reflow profile information ................................ ................................ ........................ 36 13.1 stora ge condition ................................ ................................ ................................ ................................ 36 13.1.1 moisture barrier bag before opened ................................ ................................ ..................... 36 13.1.2 moisture barrier bag open ................................ ................................ ................................ ..... 36 13.2 stencil design ................................ ................................ ................................ ................................ ..... 36 13.3 baking conditions ................................ ................................ ................................ ............................... 36 13.4 soldering and reflow condition ................................ ................................ ................................ .......... 36 13.4.1 reflow oven ................................ ................................ ................................ ........................... 36 14 reference documentation and support ................................ ................................ ... 38 15 revi sion history ................................ ................................ ................................ ........ 39
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 5 5 1 ordering information and ic marking table 1 - 1. ordering details atmel official part number (for ordering) package type ic marking ATWILC3000 - mu - t 6x6 qfn in tape and reel ATWILC3000 2 block diagram figure 2 - 1. ATWILC3000 block d iagram x x t x d i g i t a l c o r e d p d 8 0 2 . 1 1 b g n i f f t 8 0 2 . 1 1 b g n c o d i n g h o s t i n t e r f a c e m i c r o c o n t r o l l e r d a c a d c r x d i g i t a l c o r e 8 0 2 . 1 1 b g n o f d m c h a n n e l e s t i m a t i o n / e q u a l i z a t i o n 8 0 2 . 1 1 b g n f o r w a r d e r r o r c o r r e c t i o n r a m 8 0 2 . 1 1 b , g , n m a c ~ s d i o s p i x o p m u i 2 c r t c c l o c k v b a t t p l l g f s k d e m o d 8 p s k & q p s k d e m o d w i - f i / b l u e t o o t h c o e x i s t e n c e f r o n t e n d g f s k m o d u l a t o r 8 p s k & q p s k m o d f r o n t e n d b l u e t o o t h 4 . 0 m a c f r o n t e n d f r o n t e n d u a r t p c m a u d i o i n t e r f a c e g p i o
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 6 6 3 pino ut and package information 3.1 pin description ATWILC3000 is offered in an exposed pad 48 - pin qfn package. this package has an exposed paddle that must be connected to the system board ground. the qfn package pin assig nment is shown in figure 3 - 1 . the color shading is used to in dicate the pin type as follows: ? green C power ? red C analog ? blue C digital i/o ? yellow C digital input ? grey C unconnected or reserved the ATWILC3000 pin s are described in table 3 - 1 . figure 3 - 1. pin assignment
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 7 7 table 3 - 1. pin description pin # pin name pin type description 1 vddrf_rx power tuner rf rx supply 2 vddams power tuner bb supply 3 vddrf_tx power tuner rf tx supply 4 vddbatt_ppa/pa powe r battery supply for pa 5 rfiop analog wi - fi/bluetooth pos itive rf differential i/o 6 rfion analog wi - fi/bluetooth neg ative rf differential i/o 7 nc none customer no connect 8 nc none customer no connect 9 nc none customer no connect 10 nc none custo mer no connect 11 test_mode digital input test mode C customer tie to gnd 12 sdio_spi_cfg digital input tie to vddio for spi, gnd for sdio 13 resetn digital input active - low hard reset 14 gpio16 digital i/o, programmable pull - u p gpio_16/ bluetooth uart transmit data output 15 gpio15 di gital i/o, programmable pull - u p gpio_15/ bluetooth uart receive data in- put 16 gpio14 digital i/o, programmable pull - u p gpio_1 4/bluetooth uart rts output/ i 2 c slave data 17 gpio13 digital i/o, programmable pull - u p gpio_13/ b luetooth uar t cts input/i 2 c slave clock/ wi - fi uart tx d output 18 vddc power digital core power supply 19 vddio_0 power digital i/o power supply 20 gpio3 digital i/o, programmable pull - u p gpio_3/ spi flash clock output 21 gpio4 digital i/o, programmable pull - u p gpio_4/ spi flash ssn output 22 gpio5 digital i/o, programmable pull - u p gpio_5/wi - fi uart tx d output /spi flash tx output (mosi) 23 gpio6 digital i/o, programmable pull - u p gpio_6/wi - fi uart rx d input/ spi flash rx input (miso) 24 vbatt_buck power b attery supply for dc/dc converter 25 vsw power switching output of dc/dc converter 26 vreg_buck power core power from dc/dc converter 27 chip_en analog pmu enable 28 rtc_clk digital i/o, programmable pull - u p rtc clock input/gpio_1/wi - fi uart rx d input/ wi - fi uart tx d output/bt uart cts input 29 sd_clk digital i/o, programmable pull - u p sdio clock / gpio_8/wi - fi uart rx d in- put/ bt uart cts input
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 8 8 pin # pin name pin type description 30 sd_cmd/spi_sck digital i/o, programmable pull - u p sdio command/ spi clock 31 sd_dat0/spi_txd digital i/o, progr ammable pull - u p sdio data0/ spi tx data 32 sd_dat1/spi_ssn digital i/o, programmable pull - u p sdio data1/ spi slave select 33 vddio_1 power digital i/o power supply 34 sd_dat2/spi_rxd digital i/o, programmable pull - u p sdio data2/ spi rx data 35 sd_dat3 dig ital i/o, programmable pull - u p sdio data3/gpio_7/wi - fi uart tx d out- put/ bt uart rts output 36 gpio17 digital i/o, programmable pull - down gpio_17/ bluetooth pcm clock 37 gpio18 digital i/o, programmable pull - down gpio_18/ bluetooth pcm snyc 38 gpio19 digita l i/o, programmable pull - down gpio_19/ bluetooth pcm data input 39 gpio20 digital i/o, programmable pull - down gpio_20/ bluetooth pcm data output 40 irqn digital i/o, programmable pull - u p host interrupt request output/wi - fi uart rx d input/ bt uart rts output 41 gpio21 digital i/o, programma ble pull - u p gpio_21/rtc clock/wi - fi uart rx d input/wi - fi uart tx d output/bt uart rts output 42 host_wakeup digital i/o, programmable pull - u p sleep mode control/ wi - fi uart tx d out- put 43 xo_n analog crystal oscillator n 4 4 xo_p analog crystal oscillator p 45 vdd_sxdig power sx power supply 46 vdd_vco power vco power supply 47 vddio_a power tuner vddio power supply 48 tp_p analog test pin/ customer no connect 49 paddle vss power connect to system board ground 3.2 package description the ATWILC3000 qfn package information is provided in table 3 - 2 . table 3 - 2. qfn package information parameter value unit tolerance package size 5x5 mm 0.1mm qfn pad count 48 total thickness 0.85 mm +0.15/ - 0.05mm qfn pad pitch 0.40 pad width 0.25 exposed pad size 3.85x3.85
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 9 9 the ATWILC3000 40l qfn package view is shown in figure 3 - 2 . figure 3 - 2. qfn package the qfn package is a qualified green package .
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 1 0 10 4 electrical specifications 4.1 absolute rating s table 4 - 1. absolute maximum ratings characteristic symbol min . max . unit core supply voltage vddc - 0.3 1.5 v i/o supply voltage vddio - 0.3 5.0 battery supply voltage vbatt - 0.3 5.0 digital input voltage v in (1) - 0.3 vddio analog input voltage v ain (2) - 0.3 1.5 esd human body model v esdhbm - 1000, - 2000 (see notes below) +1000, +2000 (see notes below) storage temperature t a - 65 150 o c junction temperature 125 rf input power max . 23 dbm notes: 1. v in corresponds to all the digital pins. 2. v ain corresponds to th e following analog pins: vdd_rf_rx, vdd_rf_tx, vdd_ams, rfiop, rfion, xo_n, xo_p, vdd_sxdig, and vdd_vco. 3. for v esdhbm , each pin is classified as class 1, or class 2, or both: ? the class 1 pins include all the pins (both analog and digital) ? the class 2 pins are all digital pins only ? v esdhbm is 1kv for class1 pins. v esdhbm is 2kv for class2 pins 4.2 recommended operating conditions table 4 - 2. recommended operating conditions characteristic symbol min . typ . max . unit i/o supply voltage low range vddio l 1.62 1.80 2.00 v i/ o supply voltage mid - range vddio m 2.00 2.50 3.00 i/o supply voltage high range vddio h 3.00 3.30 3.60 battery supply voltage vbatt 2.5 ( 1 ) 3.6 4.2 operating temperature - 40 85 o c notes: 1. ATWILC3000 is functional across this range of voltages; however, opti mal rf performance is guaranteed for vbat in the range 3.0v < vbat < 4.2v . 2. i/o supply voltage is applied to the following pins: vddio_a, vddio. 3. battery supply voltage is applied to following pins: vdd_batt_ppa, vdd_batt_pa, and vbatt _buck.
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 1 1 11 4.3 dc electrical characteristics table 4 - 3 provides the dc characteristics for the ATWILC3000 digital pads . table 4 - 3. dc electrical characteristics vddio condition characteristic min. max. unit vddio l input low voltage v il - 0.30 0.60 v input high vo ltage v ih vddio - 0.60 vddio+0.30 output low voltage v ol 0.45 output high voltage v oh vddio - 0.50 vddio m input low voltage v il - 0.30 0.63 input high voltage v ih vddio - 0.60 vddio+0.30 output low voltage v ol 0.45 output high voltage v o h vddio - 0.50 vddio h input low voltage v il - 0.30 0.65 input high voltage v ih vddio - 0.60 vddio+0.30 (up to 3.60) output low voltage v ol 0.45 output high voltage v oh vddio - 0.50 all output loading 20 pf all digital input load 6 vddi o l p ad drive strength 1.7 2.4 ma vddio m p ad drive strength 3.4 6.5 vddio h p ad drive strength 10.6 13.5
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 1 2 12 5 clocking 5.1 crystal oscillator table 5 - 1. crystal oscillator parameters parameter min . typ . ma x. unit crystal resonant frequency 14 26 40 mhz crystal equi valent series resistance 50 150 ? stability C initial offset (1) - 100 100 ppm stability - temperature and aging - 20 20 initial offset must be calibrated to maintain 20 ppm in all operating conditions when including temperature and aging . this calibrati on is performed during final production testing . the block diagram in figure 5 - 1 (a) shows how the internal crystal oscillator (xo) is connected to the external crystal. the xo has 5pf internal capacitance on each terminal xo_p and xo_n. to bypass the crystal oscillator with an external reference, an external signal capable of driving 5pf can be applied to the xo_n terminal as shown in figure 5 - 1 (b) . figure 5 - 1. xo connections (a) cry stal oscillator is used (b) crystal oscillator is bypassed below are the electrical and performance requirements for the external clock . table 5 - 2. bypass clock specification parameter min . max . unit comments oscillation frequency 12 40 mhz must be able to drive 5 pf load @ desired frequency voltage swing 0.5 1.2 v pp must be ac coupled stability C temperature and aging - 20 +2 0 ppm phase noise - 130 dbc/hz at 10khz offset jitter(rms) <1psec based on integrated phase noise spectrum from 1khz to 1mhz a t w i l c 3 0 0 0 x o _ n x o _ p ( a ) a t w i l c 3 0 0 0 x o _ n x o _ p ( b ) e x t e r n a l c l o c k
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 1 3 13 5.2 low - power oscillator atwilc3 000 requires an external 32.768 khz clock to be used for sleep operation, which is provided through pin 28 or pin 41. the frequency accuracy of the external clock has to be within 5 00 ppm .
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 1 4 14 6 cpu and memory subsystems 6.1 processor ATWILC3000 h as a cortus aps3 32 - bit processor. this processor performs many of the mac functions, including but not limited to association, authentication, power management, security key management, and msdu aggregation/de - aggregation. in addition, the processor provi des flexibility for various modes of operation, such as sta and ap modes . 6.2 memory subsystem the aps3 core uses a 256 kb instruction/boo t rom (160 kb for 802.11 and 96 kb for bluetooth) along with a 420 kb instruction ram (128 kb for 802.11 and 292 kb for bluetoot h ), and a 128 kb data ram (64 kb for 802.11 and 64 kb for bluetooth). in addition, the device uses a 160 kb shared/exchange ram (128 kb for 802.11 and 32 kb for bluetooth), accessible by the processor and mac, which allows the processor to perform various data m anagement tasks on the tx and rx data packets . 6.3 non - volatile memory ( e fuse) ATWILC3000 has 768 bits of non - volatile efuse memory that can be read by the cpu after device reset. this non - volatile one - time - programmable memory can be used to store customer - spe cific parameters, such as 802.11 mac address, bluetooth address, and various calibration information, such as tx power, crystal frequency offset, etc., as well as other software - specific configuration parameters. the efuse is partitioned into six 128 - bit b anks. the bit map of the first and last banks is shown in figure 6 - 1 . the purpose of the first 80 bits in bank 0 and the first 56 bits in bank 5 is fixed, and the remaining bits are general - purpose software dependent bits, or r eserved for future use. currently the bluetooth address is derived from the wi - fi mac address (bt_addr=mac_addr+1). this eliminates the need to program the first 56 bits in bank 5. since each bank and each bit can be programmed independently, this allows f or several updates of the device parameters following the initial programming, e.g. updating 802.11 mac address or bluetooth address (this can be done by invalidating the last programmed bank and programming a new bank). r efer to ATWILC3000 programming gui de for the efuse programming instructions .
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 1 5 15 figure 6 - 1. e fuse bit map b a n k 0 b a n k 1 b a n k 2 b a n k 3 b a n k 4 b a n k 5 f m a c a d d r u s e d i n v a l i d v e r s i o n r e s e r v e d m a c a d d r u s e d f o g 3 1 1 4 1 u s e d t x g a i n c o r r e c t i o n u s e d f r e q . o f f s e t 1 7 4 8 8 8 1 6 1 1 5 1 2 8 b i t s f b t a d d r u s e d b t a d d r i n v a l i d v e r s i o n r e s e r v e d r e s e r v e d b t a d d r 4 8 8 1 1 3 2 1
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 1 6 16 7 wlan subsystem the wlan subsystem is composed of the media access controller (mac) and the physical layer (phy). sections 7.1 and 7.2 describe the mac and phy in detail . 7.1 mac 7.1.1 features the ATWILC3000 ieee802.11 mac supports the following functions: ? ieee 802.11b/g/n ? ieee 802.11e wmm qos edca/pcf multiple access categories traffic scheduling ? advanced ieee 802.11n feat ures: C transmission and recepti on of aggregated mpdus (a - mpdu) C transmission and reception of aggregated msdus (a - msdu) C immediate block acknowledgement C reduced interframe spacing (rifs) ? support for ieee802.11i and wfa security with key management C wep 64/128 C wpa - tkip C 128 - bit wpa2 ccmp (aes) ? support for wapi security ? advanced power management C standard 802.11 power save mode C wi - fi alliance wmm - ps (u - apsd) ? rts - cts and cts - self support ? supports either sta or ap mode in the infrastructure basic service set mode ? sup ports independent basic service set (ibss) 7.1.2 description the ATWILC3000 mac is designed to operate at low power while providing high data throughput. the ieee 802.11 mac functions are implemented with a combination of dedicated data path engines, hardwired c ontrol logic, and a low - power, high - efficiency microprocessor. the combination of dedicated logic with a programmable processor provides optimal power efficiency and real - time response while providing the flexibility to accommodate evolving standards and f uture feature enhancements. dedicated data path engines are used to implement data path functions with heavy computational requirements . for example, an fcs engine checks the crc of the transmitting and receiving packets, and a cipher engine performs all the required encryption and decryption operations for the wep, wpa - tkip, wpa2 ccmp - aes, and wapi security requirements. control functions , which have real - time requirements , are implemented using hardwired control logic modules. these logic modules offer real - time response while maintaining configurability via the processor. examples of hardwired control logic modules are the channel access control module (implements edca/hcca, beacon tx control, interframe spacing, etc.), protocol timer module (responsibl e for the network access vector, back - off timing, timing synchronization function, and slot management), mpdu handling module, aggregation/de - aggregation module, block ack controller (implements the protocol requirements for burst block communication), and tx/rx control fsms (coordinate data movement between phy - mac interface, cipher engine, and the dma interface to the tx/rx fifos) .
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 1 7 17 the mac functions implemented solely in software on the microprocessor have the following characteristics : ? functions with hi gh memory requirements or complex data structures. examples are association table management and power save queuing . ? functions with low computational load or without critical real - time requirements. examples are authentication and association . ? functions, w hich need flexibility and upgradeability. examples are beacon frame processing and qos scheduling . 7.2 phy 7.2.1 features the ATWILC3000 ieee802.11 phy supports the following functions: ? single antenna 1x1 stream in 20mhz channels ? supports ieee 802.11b dsss - cck modulation: 1, 2, 5.5, and 11mbps ? supports ieee 802.11g ofdm modulation: 6, 9, 12,18, 24, 36, 48, and 54mbps ? support s ieee 802.11n ht modulations mcs0 - 7, 20mhz, 800 and 400ns guard interval: 6.5, 7.2, 13.0, 14.4, 19.5, 21.7, 26.0, 28.9, 39.0, 43.3, 52.0, 57.8, 58.5, 65.0, and 72.2mbps ? ieee 802.11n mixed mode operation ? per packet tx power control ? advanced channel estimat ion/equalization, automatic gain control, cca, carrier/symbol recovery, and frame detection 7.2.2 description the ATWILC3000 wlan phy is designed to achieve reliable and power - efficient physical layer communi cation specified by ieee 802.11 b/g/n in single stream mode with 20mhz bandwidth. advanced algorithms have been employed to achieve maximum throughput in a real world communication environment with impairments and interference. the phy implements all the required functions such as fft, filtering, fec (viterbi decoder), frequency , and timing acquisition and tracking, channel estimation and equalization, carrier sensing and clear channel assessment, as well as the automatic gain control . 7.3 802.11 b/g/n radio performance 7.3.1 receiver performance radio p erformance under t ypical c onditions: vbatt =3.6v; vddio=3.3v; t emp . : 25c . table 7 - 1. ATWILC3000 conducted receiver performance parameter description min. typ. max. unit frequency 2,412 2,484 mhz sensitivity 802.11b 1 mbps dss - 98.0 dbm 2 mbps dss - 95.0 5.5 mbps dss - 93.0 11 mbps dss - 89.0 sensitivity 802.11g 6 mbps ofdm - 90.6 dbm 9mbps ofdm - 89.0 12mbps ofdm - 87.9
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 1 8 18 parameter description min. typ. max. unit 18mbps ofdm - 86.0 dbm 24mbps ofdm - 83.0 36mbps ofdm - 79.8 4 8mbps ofdm - 76.0 54mbps ofdm - 74.3 sensitivity 802.11n (bw=2 0mhz) mcs 0 - 89.0 dbm mcs 1 - 86.9 mcs 2 - 84.9 mcs 3 - 82.4 mcs 4 - 79.2 mcs 5 - 75.0 mcs 6 - 73.2 mcs 7 - 71.2 maximum receive signal level 1 - 11 mbps dss - 10 5 dbm 6 - 54 mbps ofdm - 10 - 3 mcs 0 C 7 - 10 - 3 adjacent cha nnel rejec- tion 1 mbps dss (30mhz offset) 50 db 11mbps dss (25mhz offset) 43 6mbps ofdm (25mhz offset) 40 54mbps ofdm (25mhz offset) 25 mcs 0 C 20mhz bw (25mhz offset) 40 mcs 7 C 20mhz bw (25mhz offset) 20 7.3.2 transmitter performance radio performance under typical c onditions: vbatt =3.6v; vddio=3.3v; t emp . : 25c . table 7 - 2. transmitter performance parameter description min. typ. max. unit frequency 2,412 2,484 mhz output power 802.11b dsss 1 mbps 19 1 dbm 802.11b dsss 11 mbps 17 1 802.11 g ofdm 54 mbps 16 1 802.11n mcs7 14 1 tx power accuracy 1.5 2 db carrier suppression 30.0 dbc notes: 1. measured at 802.11 spec compliant evm/spectral mask. 2. measured with 50 differential balun .
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 1 9 19 8 bluetooth subsystem the bluetooth subsystem implements all the mission critical real - time functions. it encodes/decodes hci packets, constructs baseband data packages , and manages and monitors connection status, slot usage, data flow, routing, segmentation, and buffer control. the bluetooth subsystem supports both conventional bluetooth as well as bluetooth low energy (ble) modes of operation. the bluetooth subsystem performs link control layer management supporting the following state s: ? standby ? connection ? page and page scan ? inquiry and inquiry scan ? sniff 8.1 bluetooth 4.0 features: ? extended inquiry response (eir) ? encryption pause/resume (epr) ? sniff sub - rating (ssr) ? secure simple pairing (ssp) ? link supervision time out (lsto) ? link managemen t protocol (lmp) ? quality of service (qos) 8.2 bluetooth low energy (ble) supports ble profiles allowing connection to advanced low energy application such as: ? smart energy ? consumer wellness ? home automation ? security ? proximity detection ? entertainment ? sports and fitness ? automotive
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 2 0 20 8.3 bluetooth radio 8.3.1 receiver performance radio performance under t ypical c onditions: vbatt =3.6v; vddio=3.3v; t emp . : 25c . table 8 - 1. ATWILC3000 bluetooth receiver performance parameter description min . typ . max . unit frequency 2,402 2,480 mhz sen sitivity ideal tx gfsk (0.1% ber) 1mbps - 93.0 dbm /4 dqpsk (0.1% ber) 2mbps - 95.6 8dpsk (0.1% ber) 3mbps - 90.0 ble (gfsk) - 96 maximum re- ceive signal level gfsk - 10 0 dbm /4 dqpsk - 10 - 5 8dpsk - 10 - 5 8.3.2 transmitter performance rad io performance under typical c onditions: vbatt =3.6v; vddio=3.3v; t emp . : 25c . table 8 - 2. ATWILC3000 bluetooth transmitter performance parameter description min . typ . max . unit frequency 2,402 2,480 mhz output power gfsk - 32 10.0 17 1 dbm /4 dqpsk - 32 10.0 17 1 8dpsk - 32 10.0 17 1 ble (gfsk) - 32 10.0 17 1 the maximum output power may require board filtering to meet spurious emission limits.
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 2 1 21 9 external interfaces ATWILC3000 external interfaces include: spi slave, sdio slave, and uart for 802.11 control and da ta trans fer; uart for bluetooth control and data transfer, and audio; pcm for bluetooth audio; i 2 c slave for control; spi master for external flash; i 2 c master for external eeprom, and general purpose input / output (gpio) pins. with the exception of the s pi slave and sdio slave host interfaces, which are selected using the dedicated sdio_spi_cfg pin, the other interfaces can be assigned to various pins by programming the corresponding pin muxing control register for each pin to a specific value between 0 a nd 6.the default values of these registers are 0, which is gpio mode. each digital i/o pin also has a programmable pull - up or pull - down. the summary of the available interfaces and their corresponding pin mux settings is shown in table 9 - 1 . for specific programming instructions refer to ATWILC3000 programming guide . table 9 - 1. pin - mux matrix of external interfaces pin name pin # pull mux 0 mux 1 mux 2 mux 3 m ux 4 mux 5 mux 6 gpio16 14 up gpio_16 o_bt_uart1_txd gpio15 15 up gpio_15 i_bt_uar t1_rxd gpio14 16 up gpio_14 o_bt_uart1_rts io_i2c_sda i_wakeup gpio13 17 up gpio_13 i_bt_uart1_cts io_i2c_scl o_wifi_uart_txd i_wakeup gpio3 20 up gpio_3 o_spi_sck_flash o_bt_uart2_txd gpio4 21 up gpio_4 o_spi_ssn_flash i_bt_uart2_rxd gpio5 22 up gpio_5 o_spi_txd_flash o_wifi_uart_txd i_wakeup gpio6 23 up gpio_6 i_spi_rxd_flash i_wifi_uart_rxd i_wakeup rtc_clk 28 up gpio_1 i_rtc_clk i_wifi_uart_rxd o_wifi_uart_txd i_bt_uart1_cts sd_clk 29 up gpio_8 i_sd_clk i_wifi_uart_rxd i_bt_uart1_cts sd_cmd/spi_sck 30 up io_sd_cmd io_spi_sck sd_dat0/spi_txd 31 up io_sd_dat0 o_spi_txd sd_dat1/spi_ssn 32 up io_sd_dat1 io_spi_ssn sd_dat2/spi_rxd 34 up io_sd_dat2 i_spi_rxd sd_dat3 35 up gpio_7 io_sd_dat3 o_wifi_u art_txd o_bt_uart1_rts gpio17 36 down gpio_17 io_bt_pcm_clk i_wakeup gpio18 37 down gpio_18 io_bt_pcm_sync i_wakeup gpio19 38 down gpio_19 i_bt_pcm_d_in i_wakeup gpio20 39 down gpio_20 o_bt_pcm_d_out i_wakeup irqn 40 up gpio_2 o_irqn i_wifi_uart_rxd o_bt_uart1_rts gpio21 41 up gpio_21 i_rtc_clk i_wifi_uart_rxd o_wifi_uart_txd o_bt_uart1_rts io_i2c_master_scl host_wakeup 42 up gpio_0 i_wakeup o_wifi_uart_txd io_i2c_master_sda 9.1 i 2 c slave interface the i 2 c slave interface, used primarily for control by the host processor, is a two - wire serial interface consisting of a serial data line (sda) on pin 16 (gpio14) and a serial clock line (scl) on pin 17 (gpio13). i 2 c slave responds to the seven bit address value 0x60. the ATWILC3000 i 2 c supports i 2 c bus version 2.1 - 2000 and can operate in standard mode (with data rates up to 100 kb/s) and fast mode (with data rates up to 400 kb/s). the i 2 c slave is a synchronous serial interface. the sda line is a bidirectional signal and changes only while the scl line is low, except for stop, start, and restart conditions. the output drivers are open - drain to perform wire - and functions on the bus. the maximum number of devices on the bus is limited by only the maximum c apacitance specification of 400 p f. data is transmitted in byte packages. for specific information, refer to the philips specification entitled the i 2 c - bus specification, version 2.1.
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 2 2 22 figure 9 - 2. i 2 c slave timing diagram table 9 - 2. i 2 c slave timing parameters parameter symbol min . max . unit remarks scl clock frequency f scl 0 400 khz scl low pulse width t wl 1.3 s scl high pulse width t wh 0.6 scl, sda fall time t hl 300 ns scl, sda rise time t lh 300 this is dictated by external components start setup time t susta 0.6 s start hold time t hdsta 0.6 sda setup time t sudat 100 ns sda hold time t hddat 0 40 slave and master default master programming option stop setup time t susto 0.6 s bus free time between stop and start t buf 1.3 glitch pulse reject t pr 0 50 ns 9.2 i 2 c master interface ATWILC3000 provides an i 2 c bus master, which is intended primarily for accessing an external eeprom memory through a software - defined protocol. the i 2 c master is a two - wire serial interface consisting of a serial data line (s da) and a serial clock line (scl). sda can be configured on pin 42 (host_wakeup), and scl can be configured on pin 41 (gpio21) . the i 2 c master interface supports three speeds: ? standard mode (100kb/s) ? fast mode (400kb/s) ? high - speed mode (3.4mb/s) the timing diagram of the i 2 c master interface is the same as that of the i 2 c slave interface (see section 9.3 ). the timing parameters of i 2 c master are shown in table 9 - 3 . t h l s d a s c l t h d s t a t w l t w h t s u d a t t p r t h d d a t t p r t p r t l h t h l t l h t s u s t o t b u f t s u s t a f s c l
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 2 3 23 table 9 - 3. i 2 c master timing parameters parame ter symbol standard mode fast mode high - speed mode unit min . max . min . max . min . max . scl clock frequency f scl 0 100 0 400 0 3400 khz scl low pulse width t wl 4.7 1.3 0.16 s scl high pulse width t wh 4 0.6 0.06 scl fall time t hlscl 300 300 10 40 ns sda fall time t hlsda 300 300 10 80 scl rise time t lhscl 1000 300 10 40 sda rise time t lhsda 1000 300 10 80 start setup time t susta 4.7 0.6 0.16 s start hold time t hdsta 4 0.6 0.16 sda setup time t sudat 250 100 10 ns sda hold time t hddat 5 40 0 70 stop setup time t susto 4 0.6 0.16 s bus free time between stop and start t buf 4.7 1.3 glitch pulse reject t pr 0 50 9.3 spi slave interface ATWILC3000 provides a serial peripheral interface (spi) that operates as a spi slave. the spi slave interface can be used for control and for serial i/o of 802.11 data. the spi slave pins are mapped as shown in table 9 - 4 . the rxd pin is same as master output, slave input (mosi), and the txd pin is s ame as master input, slave output (miso). the spi slave is a full - duplex slave - synchronous serial interface that is available immediately following reset when pin 12 (sdio_spi_cfg) is tied to vddio . table 9 - 4. spi slave interface pin mapping pin # spi function 12 cf g: must be tied to vddio 32 ssn: active low slave select 30 sck: serial clock 34 rxd: serial data receive (mosi) 31 txd: serial data transmit (miso) when the spi is not selected, i.e., when ssn is high, the spi interface will not interfere with data transfers between the serial - master and other serial - slave devices. when the serial slave is not selected, its transmitted data output is buffered, resulting in a high impedance drive onto the serial master receive line. the spi slave interface responds to a protocol that allows an external host to read or write any register in the chip as well as initiate dma transfers. for the details of the spi protocol and more specific instructions refer to ATWILC3000 programming guide.
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 2 4 24 the spi slave interface supports four standard modes as determined by the clock polarity (cpol) and clock phase (cpha) settings. these modes are illustrated in table 9 - 5 . the red lines in diagram correspond to clock phase = 0 and the blue lines correspond to clock phase = 1. table 9 - 5. spi slave modes mode cpol cpha 0 0 0 1 0 1 2 1 0 3 1 1 figure 9 - 3. spi slave clock polarity and clock phase timing the spi slave timing is provided in figure 9 - 4 . z z z z s c k c p o l = 0 c p o l = 1 s s n r x d / t x d ( m o s i / m i s o ) c p h a = 0 c p h a = 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 1 8
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 2 5 25 figure 9 - 4. spi slave timing diagram table 9 - 6. spi slave timing parameters (1) parameter symbol min. max. unit clock input frequency (2) f sck 48 mhz clock low pulse width t wl 6 ns clock high pulse width t wh 4 clock rise time t lh 0 7 clock fall time t hl 0 7 txd output delay (3) t odly 3 9 from sck fall 11 from sck rise rxd input setup time t isu 3 rxd input hold time t ihd 5 ssn input setup time t sussn 5 ssn input hold time t hdssn 5 notes: 1. timing is applicable to all spi modes . 2. maximum clock frequency specified is limited by the spi slave interface internal design; actual maximum clock frequency can be lower and depends on the specific pcb layout . 3. timing based on 15pf output loading . 9.4 spi master interface ATWILC3000 provides a spi master in terface for accessing external f lash memor y. the spi master pins are mapped as shown in table 9 - 7 . the txd pin is same as master output, slave input (mosi), and the rxd pin is same as master input, slave output (miso). the spi master interface supports all four standar d modes of clock polarity and clock p hase shown below. external spi f lash memory is accessed by a processor
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 2 6 26 programming commands to the spi master interface, which in turn initiates a spi master access to the f lash. for more specific instructions refer to ATWILC3000 programming guide . table 9 - 7. spi master interface pin mapping pin # pin name spi function 20 gpio3 sck: serial clock output 21 gpio4 sck: active low slave select output 22 gpio5 txd: serial data transmit output (mosi) 23 gpio6 rxd: serial data receive input (miso) the spi master timing is provided in figure 9 - 5 and table 9 - 8 . figure 9 - 5. spi master timing diagram table 9 - 8. spi master timing parameters ( 1 ) parameter symbol min. max. unit clock output frequency ( 2 ) f sck 20 mhz clock low pulse width t wl 19 ns clock high pulse width t wh 21 clock rise time ( 3 ) t lh 11 clock fall time (3) t hl 10 rxd input setup time t isu 24 rxd input hold time t ihd 0 ssn/txd output delay (3) t odly - 5 3 notes: 1. timing is applicable to all spi modes . 2. maximum clock frequency specified is limited by the spi master interface internal design; actual maximum clock frequency can be lower and depends on the specific pcb layout . 3. timing based on 15pf output loading . f s c k t w h t l h t h l t w l t o d l y t i s u t i h d s c k s s n , t x d r x d
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 2 7 27 9.5 sdio slave interface the ATWILC3000 sdio slave is a full speed interface. the interface supports the 1 - bit/4 - bit sd transfer mode at the clock range of 0 - 50mhz. the host can use this interface to read and write from any register wit hin the chip as well as configure the ATWILC3000 for data dma. to use this interface, pin 12 (sdio_spi_cfg) must be grounded. the sdio slave pins are mapped as shown in table 9 - 9 . table 9 - 9. sdio interface pin mapping pin # spi function 12 cfg: must be tied to ground 35 dat3: data 3 34 dat2: data 2 32 dat1: data 1 31 dat0: data 0 30 cmd: command 29 clk: clock when the sdio card is inserted into an sdio aware host, the detection of the card will be via the means described in sdio s pecification. during the normal initialization and interrogation of the card by the host, the card will identify itself as an sdio device. the host software will obtain the card information in a tuple (linked list) format and determine if that cards i/o f unction(s) are acceptable to activate. if the card is acceptable, it will be allowed to power up fully and start the i/o function(s) built into it. the sd memory card communication is based on an advanced 9 - pin interface (clock, command, and four data and three p ower lines) designed to operate at maximum operating frequency of 50mhz. the sdio slave interface has the following features: ? meets sdio card specification version 2.0 ? host clock rate variable between 0 and 50 mhz ? 1 bit/4 - bit sd bus modes supported ? a llows card to interrupt host ? responds to direct read/write (io52) and extended read/write (io53) transactions ? su pports suspend/resume operation the sdio slave interface timing is provided in figure 9 - 6 and table 9 - 10 .
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 2 8 28 figure 9 - 6. sdio slave timing diagram table 9 - 10. sdio slave timing parameters parameter symbol min. max. unit clock input frequency ( 1 ) f pp 50 mhz clock low pulse width t wl 6 ns clock high pulse width t wh 7 clock rise time t lh 0 5 clock fall time t hl 0 5 input setup time t isu 6 input hold time t ih 8 output delay ( 2 ) t odly 3 11 notes: 1. maximum clock frequency specified is limited by the sdio slave interface internal design; actual maximum c lock frequency can be lower and depends on the specific pcb layout . 2. timing based on 15pf output loading . 9.6 uart ATWILC3000 provides universal asynchronous receiver/transmitter (uart) interfaces for serial communication. the bluetooth subsystem has two uart interfaces: a 4 - pin interface for control, data transfer, and audio (bt uart1), and a 2 - pin interface for debugging (bt uart2). the 802.11 subsystem has one 2 - pin uart interface (wi - fi uart), which can be used for control, data transfer, or debugging. the uart interfaces are compatible with the rs - 232 standard, where ATWILC3000 operates as data terminal equipment (dte). the 2 - pin uart has receive and transmit pins (rxd and txd), and the 4 - pin uart has two additional pins used for flow control/handshaking: r equest to send (rts) and clear to send (cts). the pins associated with each uart interfaces can be enabled on several alternative pins by program ming their corresponding pin mux control registers (see below for available options ). also note that the uart r ts and uart cts are used for hardware flow control; they must be connected to the host mcu uart and enabled for the uart interface to be functional. the uart features programmable baud rate generation with fractional clock division, which allows transmiss ion and reception at a wide variety of standard and non - standard baud rates. the bluetooth uart s d _ c l k i n p u t s o u t p u t s f p p t w l t w h t h l t l h t i s u t i h t o d l y ( m a x ) t o d l y ( m i n )
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 2 9 29 input clock is selectable between 104mhz, 52mhz, 26mhz, and 13mhz. the clock divider value is progr ammable as 13 integer bits and three fractional bits (with 8. 0 being the smallest recommended value for normal operation). this results in the maximum supporte d baud rate of 10mhz / 8.0 = 13 mbd. the 802.11 uart input clock is selectable between 10mhz, 5mhz, 2.5mhz, and 1.25mhz. the clock divider value is programmabl e as 13 integer bits and three fractional bits (with 8.0 being the smallest recommended value for normal operation). this results in the maximum supported baud rate of 10mhz / 8.0 = 1.25 mbd. t he uart can be configured for seven or eight bit operation, with or without parity, with four different parity types (odd, even, mark, or space), and with one or two stop bits. it also has rx and tx fifos, which ensure reliable high speed reception and low software overhead transmission. fifo size is 4x 8 for both rx an d tx direction. the uart also has status registers showing the number of received characters available in the fifo and various error conditions, as well the ability to generate interrupts based on these status bits. an example of uart receiving or transmit ting a single packet is shown in figure 9 - 7 . this example shows 7 - bit data (0x45), odd parity, and two stop bits. for more specific instructions , refer to ATWILC3000 programming guide. figure 9 - 7. example of uart r x or t x packet 9.7 pcm inte rface ATWILC3000 provides a pcm/iom interface for bluetooth audio. this interface is compatible with industry standard pcm and iom2 compliant devices, such as audio codecs, line interfaces, tdm switches, and others. the pcm audio interface supports both ma ster and slave modes, full duplex operation, mono , and stereo. the interface operates at 8khz frame rate and supports bit rates up to 512 bits/frame (4.096mbps). the pcm interface pins are mapped as shown in table 9 - 11 . table 9 - 11. atwilc3 000 pcm interface pin mapping pin # pcm function 36 clk: bi - directional clock input/output 37 sync: bi - directional frame sync (mono) or left - right channel identifier (stereo) 38 d_in: serial data input 39 d_out: serial data output 9.8 gpios 18 general pur pose input/ output (gpio) pins, labeled gpio 0 - 8 and 13 - 21, are available to allow for application specific functions. each gpio pin can be programmed as an input (the value of the pin can be read by the host or internal processor) or as an output (the outp ut values can be programmed by the host or internal processor), where the default mode after power - up is input. gpios 7 and 8 are only available when the host does not use the sdio interface, which shares two of its pins with these gpios. therefore, for sd io - based applications, 16 gpios (0 - 6 and 13 - 21) are available. for more specific instructions refer to ATWILC3000 programming guide .
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 3 0 30 10 power management 10.1 power architecture ATWILC3000 uses an innovative power architecture to eliminate the need for external r egulators and reduce the number of off - chip components. this architecture is shown in figure 10 - 1 . the power management unit (pmu) has a dc/dc converter that converts vbat to the core supply used by the digital and rf/ams block s. in table 10 - 1 the typical values for the digital and rf /ams core voltages are shown . the pa and e fuse are supplied by dedicated ldos, and the vco is supplied by a separate ldo structure . figure 10 - 1. power architecture vbatt _ buck off - chip lc rf / ams core sleep osc rf / ams core voltage vsw vreg _ buck vdd _ ams , vdd _ rf , vdd _ sxdig ldo 1 vddio _ a vdd _ vco ldo 2 ~ vdd _ batt 1 . 2 v 1 . 0 v chip _ en efuse ldo sx digital core dc / dc converter efuse pa pmu rf / ams digital vddc dig core ldo 2 . 5 v pads vddio sleep ldo digital core voltage dcdc _ ena ena vin vout ena ena vbatt vddio
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 3 1 31 table 10 - 1. pmu output voltages parameter typical rf/ams core voltage (vreg_buck) 1.3v digital core voltage (vddc) 1.1v the power connections shown provide a conceptual framework for understanding the ATWILC3000 power architecture. r efer to the reference design for an example of power supply connections, including proper isolation of the supplies used by the digital and rf/ams blocks . 10.2 power consumption 10.2.1 description of device states ATWILC3000 has several d evices s tates: ? on_ wifi_ transmit C device is activel y transmitting an 802.11 signal ? on_ wifi_ receive C device is actively receiving an 802.11 signal ? on_bt_transmit C device is actively transmitting a bluetooth signal ? on_bt_receive C device is active ly receiving a bluetooth signal ? on_doze C device is on but is neither transmitting nor receiving ? power_down C device core supply off (leakage) the following pins are used to switch between the on and power_down states: ? chip_en C device pin (pin #27) used to enable dc/dc converter ? vddio C i/o supply voltag e from external supply in the on states, vddio is on and chip_en is high (at vddio voltage level). to switch between the on states and power_down state chip_en has to change between high and low (gnd) voltage. when vddio is off and chip_en is low, the chip is powered off with minimal leakage (also see section 10.2.3 ). 10.2.2 current consumption in various device states table 10 - 2. current consumption device state code rate output power, dbm power consumption (1) i vbat i vddio o n_ wifi_ transmit 802.11b 1mbps 19.2 325 ma 2.7 ma 802.11b 11mbps 20.1 322 ma 2.7 ma 802.11g 6mbps 17.8 298 ma 2.7 ma 802.11g 54mbps 16.2 280 ma 2.7 ma 802.11n mcs 0 19.5 295 ma 2.7 ma 802.11n mcs 7 15.3 2 81 ma 2.7 ma on_ wifi_ receive 802.11b 1mbps n/a 83.7 ma 2.5 ma 802.11b 11mbps n/a 84.9 ma 2.5 ma 802.11g 6mbps n/a 85.8 ma 2.5 ma 802.11g 54mbps n/a 90.1 ma 2.5 ma
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 3 2 32 device state code rate output power, dbm power consumption (1) i vbat i vddio 802.11n mcs 0 n/a 86 ma 2.5 ma 802.11n mcs 7 n/a 91.8 ma 2.5 ma on_ bt_ transmit ble 4.0 1mbps 8 1 10 ma <2.5 ma on_ bt_ receive ble 4.0 1mbps n/a <45 ma <2.5 ma doze n/a n/a <0. 7 ma <7 a power_down n/a n/a <0.5 a <0. 2 a conditions: vbat @3.6v , vddio @ 2 .8v , 25c . 10.2.3 restrictions for power states when no power supplied to the device, i.e., the dc/dc converter output and vddio are both off (at ground potential). in this case, a voltage cannot be applied to the device pins because each pin contains an esd diode from the pin to supply. this diode will turn on when voltage higher than one diode - drop is supplied to the pin. if a voltage must be applied to the signal pads while the chip is in a low power state, the vddio supply must be on, so the sleep or power_down state must be used. similarly, to prevent the pin - to - ground diode from turning on, do not apply a voltage that is more than one d iode - drop below ground to any pin. 10.3 power - up/down sequence the power - up/down sequence for ATWILC3000 is shown in figure 10 - 2 . the timing parameters are provided in table 10 - 3 . figure 10 - 2. power up/d own sequence v b a t t v d d i o c h i p _ e n r e s e t n t a t b t c x o c l o c k t b ' t a ' t c '
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 3 3 33 table 10 - 3. power - up/d own sequence timing parameter min . max . unit description notes t a 0 m s v bat rise to vddio rise vbat and vddio can rise simultane- ously or can be tied together. vddio must not rise before vbat. t b 0 v ddio rise to chip_en rise chip_en must not rise before vddio. chip_en must be driven high or low, not left floating. t c 5 chip_en rise to resetn rise this delay is needed because xo clock must stabilize before resetn removal. resetn must be driven high or low, not left floating. t a 0 vddio fall to vbat fall vbat and vddio can fall simultane- ously or can be tied together. vbat must not fall before vddio. t b 0 chip_en fall to vddio fall vddio must not fall before chip_en. chip_en and resetn can fal l simulta- neously. t c 0 resetn fall to vddio fall vddio must not fall before resetn. resetn and chip_en can fall simulta- neously. 10.4 digital i/o pin behavior during power - up sequences table 10 - 4 represents digital i / o pin state s corresponding to device power modes . table 10 - 4. digital i/o pin behavior in different device states device state vddio chip_en resetn output driver input driver pull up/down resistor ( 1 ) power_down: core supply off high low low disabled (hi - z) disabled disabled p ower - on reset: core supply on, hard reset on high high low disabled (hi - z) disabled enabled power - on default: core supply on, device out of reset but not pro- grammed yet high high high disabled (hi - z) enabled enabled on_doze/ on_transmit/ on_receive: core supply on, device programmed by firmware high high high programmed by firmware for each pin: ena- bled or disa- bled opposite of output driver state programmed by firmware for each pin: ena- bled or disabled the programmable pull - up/pul l - down resistor value i s 96k? 10% .
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 3 4 34 11 reference design the ATWILC3000 reference design schematic is shown in figure 11 - 1 . figure 11 - 1. ATWILC3000 reference schematic
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 3 5 35 12 reference design guidelines ? rfiop an d rfion pins must be ac coupled ? it is recommended that the b alun is located right next to the pins C if this is not possible, rfiop and rfion should be routed as 50 ? differential pair to the balun ? ATWILC3000 provides programmable pu ll - up resistors on various pins (see table 3 - 1 ) . the pu rpose of these resistors is to keep any unused input pins from floating which can cause excess current to flow through the inp ut buffer from the vddio supply . any unused pin on the device should leave these pull - up resistors ena bled so the pin will not flo at . the default state at power up is for the pull - up resistor to be enabled. however, any pin, which is used, should have the pull - up resistor disabled. the reason for this is that if any pins are driven to a low level while the device is in the low power s leep state, current will flow from the vddio supply through the pull - up resistors, increasing the current consumption of the module. since the value of the pull - u p resistor is approximately 100k ? , the current through any pull - up resistor that is being driv en low will be vddio/100k. for vddio = 3.3v, the current would be approximately 33 a . pins which are used and have had the programmable pull - up resistor disabled should always be actively driven to either a high or low lev el and not be allowed to float ? if sdio interface is used, each sdio pin should use a 70? resistor in series for rf noise filtering ? r efer to ATWILC3000 programming guide for information on enabling/disabling the programmable pull - up resistors
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 3 6 36 13 reflow profile information this c hapter provide s guidelines for reflow processes in getting the atmel module sold ered to the customers design. 13.1 storage condition 13.1.1 moisture barrier bag before opened a moisture barrier bag must be stored in a temperature of less than 30c with humidity under 85% rh. the calculated shelf life for the dry - packed product shall be 12 months from the date the bag is sealed. 13.1.2 moisture barrier bag open humidity indicator cards must be blue, < 30%. 13.2 stencil design the recommended stencil is laser - cut, stainless - steel type with thi ckness of 100m to 130m and approximately a 1:1 ratio of stencil opening to pad dimension. to improve paste release, a positive taper with bottom opening 25m larger than the top can be utilized. local manufacturing experience may find other combinations of stencil thickness and aperture size to get good results. 13.3 baking conditions this module is rated at msl level 3. after sealed bag is opened, no baking is required within 168 hours so long a s the devices are held at 30 c/60% rh or stored at <10% rh. the module will require baking before mounting if: ? the sealed bag has been open for > 168 hours ? humi dity indicator card reads >10% ? sips need to be baked for 8 hours at 125 c 13.4 soldering and reflow condition 13.4.1 reflow oven it is strongly recommended that a reflow oven equipped with more heating zones and nitrogen atmosphere be used for lead - free assembly. nitrogen atmosphere has shown to improve the wet - ability and reduce temperature gradient across the board. it can also enhance the appearance of the solde r joints by reducing the effects of oxidation. the following bullet items should also be o bserved in the reflow process: ? some recommended pastes include nc - smq ? 230 flux and indalloy ? 241 solder paste made up of 95.5 sn/3.8 ag/0.7 cu or senju n705 - grn336 0 - k2 - v type 3, no clean paste ? allowable reflow soldering times: 3 times based on the following reflow soldering profile (see figure 13 - 1 ) ? temperature profile: reflow soldering shall be done according to the fo llowing temperature profile (see figure 13 - 1 ) ? peak temp . : 250c
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 3 7 37 figure 13 - 1. solder reflow profile
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 3 8 38 14 reference documentation and support atmel offers a set of collateral documentation to ease integration and device ra mp. the following list of documents available on atmel web or integrated into development tools. to enable fast development contact your local fae or visit the http://www.atmel.com/ . title content datasheet this d ocum ent design files package user guide, sche matic, pcb layout, gerber, bom, and system notes on: rf/radio full test re- port, radiation pattern, design guidelines, temperature performance, esd. platform getting started guide how to use package: out of the box starting guide, hw limitations, and notes, sw quick start guidelines . hw design guide best practices and recommendations to design a board with the product, i ncluding: antenna design for wi - fi (layout recommendations, types of antennas, impedance matchin g, using a power ampli- fier etc . ), spi/uart protocol between wi - fi soc and the host mcu. sw design guide integration guide with clear description of: high level arch, overview on how to write a networking application, list all api, parameters, and structur es. features of the device, spi/handshake protocol between device and host mcu, with flow/se- quence/state diagram, timing. sw program- mer guide explain in details the flow chart and how to use each api to implement all generic use cases (e.g. start ap, star t sta, provisioning, udp, tcp, http, tls, p2p, errors management, connection/trans- f er recovery mechanism/state dia gram) - usage and sample application note . for a complete listin g of development - support tools and documentation, visit http://www.atmel.com/ , or contact the nearest atmel field representative.
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 3 9 39 15 revision history doc rev. date comments 42390d 05/2016 1. updated features, bluetooth to say bluetooth 4.0 (basic rate, enhanced rate, and ble) . added bluetooth cert ifications 2. replaced vbatt with vbat to match schematics. 3. revised package information in table 3 - 2 . 4. revised ppm values from 200 to 500ppm in chapter 5 . 5. revised table 7 - 2 transmitter performance values and note 2 . 6. revised the values and note in table 8 - 2 7. revised spi slave timing parameters in table 9 - 6 . 8. revised spi master timing parameters in table 9 - 8 . 9. revised sdio slave timing parameters in table 9 - 10 . 10. add text in s ection 9.6 regarding flow control usage. 11. revised current consumption values in table 10 - 2 . 12. updated package drawing to include solder paddle pad in figure 3 - 2 . 13. added reflow profile in c hapter 13 . 14. revised tolerance for thickness in table 3 - 2 for qfn package information. 15. added footnote for pull - up/pull - down ohm value in table 10 - 4 . 42390c 0 7 /2015 1. modified sections 10.2.1 and 10.2.2 to add new current consumption numbers , update state names , and correct some typos 2. fixed typos for spi slave interface timing in table 9 - 6 3. fixed typos for battery supply name: changed from vbat to vbatt 4. corrected pmu output voltages in table 10 - 1 5. updated reference schematic drawing in section 11 6. added comment regarding resistors on sdio pins in section 12 7. updated power architecture drawing in section 10.1 8 . added pad drive strength in table 4 - 3 and removed the note under table 3 - 1 9. updated operating temperature in the feature list 10. corrected current in power_down state in table 10 - 2 1 1 . miscellaneous minor formatting and content corrections 42390b 03/2015 ds update new atmel format . 42390 a 01 /201 5 initial document release.
atwilc30 00 single chip ieee 802.11 b/g/n link controller with integrated bluetooth 4.0 [ datasheet ] atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 4 0 40 atmel corporation 1600 technolog y drive, san jose, ca 95110 usa t: (+1)(408) 441.0311 f: (+1)(408) 436.4200 www.atmel.com ? 2016 atmel corporation. / rev.: atmel - 42390d - ATWILC3000 - mut - smartconnect - datasheet _ 05 /2016 . atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , and other s are registered trademarks or trademarks of atmel corporation in u.s. and other countries. other terms and product na mes may be trademarks of others. disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and cond itions of sales located on the atmel website, atme l assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non - infringement. in no event s hall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without lim itation, damages for loss and profits, business interruption, or loss of information) arising out of the use or inability to use th is document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accurac y or completeness of the contents of this document and reserves the right to make changes to specificati ons and products descriptions at any time without notice. atmel does not make any commitment to update the information contained herein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, auto motive appli cations. atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. safety - critical, military, and automotive applications disclaimer: atmel products are not designed for and will n ot be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (safety - critical applications) without an atmel officer's specific written consent. safety - cr itical applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems. atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by atmel as military - grade. atmel products are not designed nor intended for use in automotive applications unless specifically designated by atmel as automotive - grade.

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